DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

APARNA A; VIGNESWARAN T

doi:10.22159/ajpcr.2017.v10s1.19564

Authors

APARNA A Department of Electronics and Communication, VIT University, Chennai Campus, Chennai, Tamil Nadu, India
VIGNESWARAN T Department of Electronics and Communication, VIT University, Chennai Campus, Chennai, Tamil Nadu, India

DOI:

https://doi.org/10.22159/ajpcr.2017.v10s1.19564

Keywords:

Finite impulse response filter, Distributed arithmetic, Digital signal processing, Multiplier-less

Abstract

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmableÂ gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filterÂ is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental componentsÂ in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of lowÂ power and high speed various embedded applications.

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