EFFICIENT FINITE IMPULSE RESPONSE FILTER ARCHITECTURE USING MULTIPLE CONSTANT MULTIPLICATION AND COMMON SUB-EXPRESSION ELIMINATION TECHNIQUES

Bhargav Shukla; Augusta Sophy Beulet

doi:10.22159/ajpcr.2017.v10s1.19752

Authors

Bhargav Shukla School of Electronics Engineering, VIT University, Chennai, Tamil Nadu
Augusta Sophy Beulet School of Electronics Engineering, VIT University, Chennai, Tamil Nadu

DOI:

https://doi.org/10.22159/ajpcr.2017.v10s1.19752

Keywords:

Filters, Multiple constant multiplication, Common sub-expression elimination, Finite impulse response, Canonical signed digit, Binary signed digit, Horizontal sub-expression elimination, Vertical sub-expression elimination

Abstract

This paper introduces the computationally efficient, low power, high-speed partial reconfigurable finite impulse response (FIR) filter design using
multiple constant multiplication technique (MCM). The complexity of many digital signal processing (DSP) systems is reduced by MCM operation. For
the better performance of DSP systems, MCM operation is not sufficient. To get better results, some other operations are used with MCM. That's why,
this paper introduces a common sub-expression elimination operation of FIR filter design can be solved by decreasing the number of operators. Using
these techniques shows the efficiency by reducing area when compared to previously used algorithms designed.

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