FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF THE DYNAMIC TIME WARPING ALGORITHM FOR SPEECH RECOGNITION

Mitali Bhojwani; John Sahaya Rani Alex

doi:10.22159/ajpcr.2017.v10s1.19753

Authors

Mitali Bhojwani School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India
John Sahaya Rani Alex School of Electronics Engineering, VIT University, Chennai, Tamil Nadu, India

DOI:

https://doi.org/10.22159/ajpcr.2017.v10s1.19753

Keywords:

Dynamic time warping, Field-programmable gate array, Speech recognition

Abstract

Objective of this research is to implement a speech recognition algorithm in smaller form factor device. Speech recognition is an extensively used in
mobile and in numerous consumer electronics devices. Dynamic time warping (DTW) method which is based on dynamic programming is chosen to
be implemented for speech recognition because of the latest trend in evolving computing power. Implementation of DTW in field-programmable gate
array is chosen for its featured flexibility, parallelization and shorter time to market. The above algorithm is implemented using Verilog on Xilinx ISE.
The warping cost is less if the similarity is found and is more for dissimilar sequences which is verified in the simulation output. The results indicate
that real time implementation of DTW based speech recognition could be done in future.

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